FIELD OF THE INVENTION
The invention relates to a method of producing a barrier layer on a contact plug which is disposed in a semiconductor body and that extends substantially to a main surface of the semiconductor body. The invention also pertains to a semiconductor component with a barrier layer of this type.
Semiconductor memories consist of a plurality of memory cells, each of which have a selection transistor and a storage capacitor connected to the selection transistor. A fundamental problem in the continuing miniaturization of integrated circuits resides in the integration of these storage capacitors. Since the capacitance is proportional to their cross-sectional area and therefore to the substrate surface area which they occupy, they cannot be miniaturized in the same way as, for example, transistors.
One approach to solving this problem is to no longer use a reverse-biased pn-junction or the insulator layer (silicon dioxide and/or silicon nitride) always present in MIS or MOS technology as the dielectric of the storage capacitor, but instead to apply a dielectric layer of a material having higher dielectric constant to the semiconductor substrate specifically for this purpose.
Materials which have a high dielectric constant can be classified according to the following table in two different groups:
TABLE ______________________________________ Paraelectric materials Ferroelectric materials ______________________________________ Property Only high .epsilon., linear High .epsilon. + nonlinear relationship between relationship between polarization of the polarization of the dielectric dielectric and applied and applied electric field. electric field Hysteresis loop between polarization and E-field. Examples BST (= (Ba,Sr)TiO.sub.3 PZT (= Pb(Zr, Ti)O.sub.3, SBT (+ SrBi.sub.2 Ta.sub.2 O.sub.9), BT (= Bi.sub.4 Ti.sub.3 O.sub.11) Application Future DRAM generations FRAM and Smart cards, both of which are non-volatile memories. Information By charging By polarization storage Advantages no refresh needed information retained after supply voltage turned off ______________________________________
FRAMs represent a further development of DRAMs: by virtue of the fact that the dielectric or paraelectric material between the plates is replaced by a ferroelectric, the information is stored as polarization and is retained after the power source has been turned off. The basic structure (selection transistor, stack capacitor, etc.) is the same in the case of DRAM and FRAM--as are many of the integration problems. For this reason, it is expedient, for example, to replace Si.sub.3 N.sub.4 by BST, which has an .epsilon. of up to 600.
However, problems arise in the processing of oxide ceramic materials because the layer materials are generally deposited in an atmosphere containing oxygen. The result of this is that the electrode material next to the dielectric is oxidized, and this has a detrimental effect on its conductivity and therefore the reliability of the overall circuit. In particular, the contact plugs of the semiconductor body are compromised. This problem also arises if the so-called stack principle is adopted for the storage capacitors, a principle in which the lower electrode, which may for example consist of platinum, is in direct contact with the contact plug. The upper electrode, which for example also consists of platinum, is designed as a so-called common plate.
The representative prior art is illustrated in the sectional detail of a semiconductor component of that type in FIG. 6. The semiconductor body is denoted by the reference numeral 10 and the contact plugs by the reference numeral 16. Between the contact plugs 16 there is an oxide layer, for example TEOS. Further, doped wells 14, with which partial contact is made by the contact plugs 16 and bit lines 18, are embedded in the semiconductor body 10. Between two wells 14 there is a word line 17, in each case embedded in the oxide layer 12. The two electrode layers 26,24, with a dielectric layer 22 in between, are arranged on the upper main surface of the semiconductor body 10 in order to form the storage capacitors. The upper electrode layer is denoted by the reference numeral 26, and the lower, structured electrode layer by the reference numeral 24. After the lower electrode 24 has been processed (deposition, structuring, etc.), the dielectric material is deposited. This may, for example, be done by a physical deposition process, for example sputtering. Preferably, however, a chemical vapor deposition (CVD process) is used for this. As a rule, oxygen is present during the deposition of the dielectric. However, the material obtained in this way does not generally have optimum electrical properties. These are only obtained if it is thermally treated at fairly high temperature in 0.sub.2, for example BST at 650.degree. C., SBT at 700.degree. to 800.degree. C. The upper electrode 26 is then deposited. To optimize the electrical properties further, another thermal treatment step generally takes place at the above-mentioned temperatures in 0.sub.2. Particular problems arise in this case owing to the diffusion of oxygen through the lower, structured electrode 24, which may disadvantageously lead to oxidation of the contact plug material and therefore to an interruption of the barrier layer between the contact plug 16 and the lower electrode 24. The conductivity and therefore the reliability of the overall circuit in the semiconductor body is therefore considerably impaired. In order to prevent this, barrier layers must be inserted between the contact plugs and the lower electrodes. The interposition of a barrier layer 28 of this type is represented schematically in FIG. 7.
During the production of the above-mentioned stack capacitors, both the lower electrodes 24 and the barrier layers 28 need to be structured. Because the barrier materials are especially stable, considerable problems may arise during these structuring processes. For this reason, the barrier layers have to date usually been deposited in a sputtering process and then subsequently structured separately, for example by physical etching.